GaN开关器件因其材料特性优异，在电力电子领域现已得到广泛应用。由于表面陷阱以及缓冲层陷阱的存在，现阶段的GaN器件存在动态导通电阻衰退问题。在器件开通之后，其导通电阻将会高于其静态导通电阻值，并随着开通时间的增加而逐渐恢复。

目前对于GaN器件动态导通电阻的学术研究存在着一定的局限：（1）在具有半桥结构的拓扑中，构成半桥桥臂的一对开关管可能分别工作于第一象限和第三象限，而现有的测试电路多设计于第一象限模式进行测试；（2）目前市场上的GaN器件主要分为肖特基门极和欧姆门极两种结构，它们在不同工况下的动态电阻表现需要分别评估。

为应对现有研究的局限性，ZJU-PMIC团队提出了集第一象限、第三象限测试于一体的全象限GaN器件动态导通电阻测试电路，并配套提出了一种准确有效的动态电阻测试方法，以评估不同技术路线的600/650V GaN器件的动态性能。

GaN devices have been widely used in the field of power electronics due to their excellent material properties. Due to the presence of surface traps and buffer layer traps, GaN devices suffer from dynamic resistance degradation. After the device is turned on, its on-resistance will be higher than its static resistance value and gradually recover with increasing on-time. At present, there are certain limitations in academic research on the dynamic on-resistance of GaN devices: (1) in topologies with a half bridge structure, a pair of switching tubes that make up the half bridge arm may operate in the first and third quadrants respectively, while existing testing circuits are mostly designed for testing in the first quadrant mode; (2) At present, GaN devices are mainly divided into two structures: Schottky gate and Ohmic gate, and their dynamic resistance performance under different operating conditions needs to be evaluated separately.

To address the limitations of existing research, ZJU-PMIC has proposed a full quadrant GaN device dynamic conduction resistance testing circuit that integrates first and third quadrant testing, and has also proposed an accurate and effective dynamic resistance testing method to evaluate the dynamic performance of 600/650V GaN devices with different technical routes.