Accomplishments

Research on Combined Device and Winding Loss Model in DCX Circuit(Aug.2024)

2024-08-28

Improving the conversion efficiency of converters in battery energy storage systems is of great significance to save energy and enhance economic value. In order to improve the efficiency of isolated step-up DC-DC converters in the system, resonant converters fixed at the switching frequency are widely used (DCX), which are mainly responsible for providing voltage gain and power, supplemented by a voltage regulation circuit (R). In DCX circuit, device conduction loss and winding loss (i.e., copper loss) account for the majority. Both can essentially be seen as conduction loss, with the difference being that the material through which the current flows. Device loss is the flow of current through the semiconductor, while winding loss is the flow of current through the copper. In this work, a circuit design method that comprehensively considers the device conduction loss and winding loss is proposed, and a combined conduction loss model suitable for DCX circuit is […]

Voltage Balance Control for Three Phase MISN PFC Converter(Aug.2024)

2024-08-01

The three-phase MISN-PFC multilevel converter has the potential to deliver enhanced efficiency and a higher power density. In contrast to other multilevel converters, the MISN converter uniquely integrates the benefits of a single output bus with modular design, which is conducive to the implementation of redundancy protection or hot standby in multilevel networks, thereby enhancing the overall reliability of the converter. Despite these advantages, the MISN converter presents a significant challenge in maintaining voltage balance across its multiple cells. This research conducts a thorough modal analysis to construct a mathematical model that delineates the influence of duty cycle deviation on the voltage imbalance within the MISN converter. The analysis reveals a direct correlation between the magnitude of duty cycle deviation and the severity of voltage imbalance. To address this issue and ensure voltage equalization even in the presence of considerable duty cycle deviation, a novel voltage balancing control strategy is introduced […]

A direct current (DC) differential method for high-frequency magnetic core loss measurement(2024.04)

2024-04-14

提出了一种测试高频磁芯损耗的直流差分方法。该方法是对测试磁芯损耗的传统直流方法的改进，克服了其无法区分磁损和铜损的显著缺点。所提出的测试方法通过增加绕组、在不同绕组配置下进行测试，可以精确地测量磁芯的高频损耗（>MHz），尤其适用于低磁导率或开气隙的磁芯。根据所提出的方法，搭建了自动化的测试平台，可以方便地对磁芯损耗进行测试。 A direct current (DC) differential method for high-frequency magnetic core loss measurement is proposed in this study. This method is an improvement over traditional DC methods for testing core losses, overcoming their significant drawback of being unable to distinguish between magnetic losses and copper losses. The proposed testing method achieves precise measurement of high-frequency (>MHz) core losses by increasing the number of windings and conducting tests under different winding configurations. It is especially suitable for magnetic cores with low magnetic permeability or air gaps. An automated testing platform based on this method has been developed, facilitating convenient testing of magnetic core losses. Fig. 1 the principles of the proposed DC differential method. Fig. 2 Measurement results of NPX60 material, size of 23.57 mm × 14.4 mm × 8.89 mm, 25 ℃

GaN器件动态电阻高温测试平台及方法（2024年4月）

2024-04-01

GaN开关器件因其材料特性优异，在电力电子领域现已得到广泛应用。由于表面陷阱以及缓冲层陷阱的存在，现阶段的GaN器件存在动态导通电阻衰退问题。在器件开通之后，其导通电阻将会高于其静态导通电阻值，并随着开通时间的增加而逐渐恢复。目前大多数动态电阻测量工作处于室温，考虑到GaN器件正常工作时会处于较高的温度，本工作基于热阻模型搭建了适用于GaN器件高温动态电阻测试的平台，通过监测器件外壳的壳温来获取器件的结温，采用多组双脉冲的测试方法，测量得到了GaN器件在不同结温下的动态电阻数据。 GaN devices have been widely used in the field of power electronics due to their excellent material properties. Due to the presence of surface traps and buffer layer traps, GaN devices suffer from dynamic resistance degradation. After the device is turned on, its on-resistance will be higher than its static resistance value and gradually recover with increasing on-time. At present, most dynamic resistance measurements are conducted at room temperature. Considering that GaN devices work normally at higher temperatures, this work builds a bench suitable for high-temperature dynamic resistance testing of GaN devices based on a thermal resistance model. The junction temperature of the device is obtained by monitoring the case temperature of the device case. Multi-group Double Pulse Test (MGDPT) method is used to measure the dynamic resistance data of GaN devices at different junction temperatures. Fig. 1 Heating Scheme Fig. 2 Thermal Resistance Model Fig. 3 Stress-Controlled Test Bench Fig. 4 MGDPT Test Waveform 往期相关成果：全象限GaN器件动态导通电阻测试方案及其测试电路（2023年12月）

基于多层烧结工艺的功率器件3D集成封装的关键技术（2024年4月）

2024-10-14

集成陶瓷敷铜板、功率器件以及PCB板的3D集成封装可同时实现低杂散电感以及低热阻，同时可集成散热器、栅极驱动、解耦电容等元件。若采用传统的多级阶梯温度回流焊接工艺实现该封装中的多层连接层，模块的可靠性会显著降低；而且高压GaN HEMT器件表面极小的电极面积、间距也给封装带来了极大挑战。本工作提出基烧结工艺的封装方式，使每层连接层的工艺温度保持相同，同时利用柔性PCB板及精细烧结技术将高压GaN HEMT器件表面电极及间距扩大化，显著地提升了封装的可靠性。此外，模块信号输入端口应保持较低的阻抗以减小功率器件开关时带来的误动作，并通过仿真与测试互相辅助的方法来检测高集成3D封装中的器件开关特性。 The 3D-integrated packaging of integrated ceramic substrate, power devices, and PCB boards can simultaneously achieve low stray inductance and low thermal resistance, while also integrating components such as heatsink, gate driver, and decoupling capacitors. If the traditional multi-temperature reflow soldering processes is used to achieve multi-layer connections in this package, the reliability will be significantly reduced; Moreover, the extremely small electrodes area and spacing of high-voltage GaN HEMT devices pose great challenges to packaging. This work proposes a packaging method based on sintering technology, which maintains the same process temperature for each connecting layer. At the same time, flexible PCB boards and refined sintering technology are used to expand the surface electrodes and spacing of high-voltage GaN HEMT devices, significantly improving the reliability of packaging. In addition, the module signal input port should maintain a low impedance to reduce fault action caused by power device switching, and […]

元胞化MHz高效高功率密度380V-12V DCX（2024年3月）

本工作利用低压Si器件低NFoM特性，降低串联谐振电路软开关的励磁电流，从而降低导通损耗并提升效率。采用元胞化后由于器件数量的增多，驱动损耗也相应增大，谐振驱动电路利用电感与主电路MOS管的栅极电容谐振，在管子关断时将能量由栅极电容转移至励磁电感，从而实现能量回收。对于传统UI型磁芯，磁芯高度（3mm）高于器件高度（1.5mm），从而导致空间浪费，本工作提出一种多窗口磁芯结构，将磁芯高度减半，从而提高了功率密度。在绕组方面，绕组未交叠部分会大幅增加该部分的涡流损耗，本工作通过绕组优化缩短了原边端子长度，并实现副边端子交叠，从而降低了绕组损耗，提高效率。 This work using the low NFoM character of low voltage Si device to reduce the magnetizing current of series resonant circuit. In this case, conduction loss can be reduced, while efficiency is improved. However, using cellular circuit leads to increase of the number of devices, which causes larger driving loss. By the resonance of inductance and gate capacitance, the energy of gate capacitance can be transferred to magnetizing inductance to realize energy recovery. For traditional UI core, the height of the core (3mm) is higher than device (1.5mm), which caused the waste of space, this work proposed a muti-window core structure, which can reduce the height of the core by half and increase power density. As for winding, the terminal part which is not interleaving occupies large eddy loss. By the optimization of winding, the length of primary terminal is shorten, while the secondary terminal is better interleaving. These two measures […]

240W高效高功率密度PD适配器设计及验证（2024年6月）

为了满足现代人们对于快充和便携性的需求，适配电源的效率和功率密度成为关键指标。现有方案在低压输入时，面临PFC电流纹波导致样机效率下降的问题，而设计采用的高压器件NFoM较大也导致变换器频率难以提升。为设计宽范围高效高密度AC/DC适配电源，本工作引入多电平和元胞化技术构建了三级拓扑架构，利用低压器件低NFoM特性大幅降低高频损耗。 To meet the modern demands for fast charging and portability, the efficiency and power density of adapters have become key indicators. The existing topology is faced with the problem that the efficiency of the prototype decreases due to PFC current ripple when the input is low voltage. Meanwhile, the high-voltage devices used in existing solutions have a relatively large New Figure of Merit (NFoM, NFoM=RdsonCo(tr)), which hinders frequency improvement. In order to design wide output range, high-efficient and high-density AC/DC adapters, multi-level and cell-based technologies are introduced to reduce high-frequency losses by utilizing low-voltage devices with low NFoM characteristics. 往期相关成果： 1. 240W高效高密度PD适配器样机（2023年12月） 2. 240W适配器的高频开关共模噪声分析与抑制（2023年12月）

Efficiency Optimization of Isolated Step-up Bidirectional DC-DC Converter for Energy Storage System（Apr.2024）

2024-04-24

为了满足低压电池储能系统对变换器高效高密度的需求，构建了第一版以低压低NFoM (Rdson*Cotr)Si器件为开关管的元胞化RDCX样机，在额定点(Vbat=48V)工作时满载效率为97.9%。为进一步提高变换器额定点满载效率至98.5%，通过并联绕组和器件(降低电阻R)、同时使用具有相同Rdson但NFoM值更小的低压GaN器件(降低电容C)，不仅器件上的导通损耗和绕组的直流损耗可以降低，而且绕组的交流损耗也有所下降。经实验验证，当前第二版样机的DCX部分满载效率相比第一版样机有较大提升。具体为：额定点48V输入时，满载效率为98.7%，提高了0.6%；40V输入时，满载效率为98.5%，提高了0.6%；60V输入时，满载效率为98.7%，提高了0.5%。 In order to meet the requirements of low-voltage battery energy storage system for high efficiency and high density of converters, the 1st generation of cellular RDCX prototype with low-voltage and low-NFoM (Rdson*Cotr) Si device as switches was constructed, and the full-load efficiency was 97.9% when at the rated point (Vbat=48V). For further increasing the full-load efficiency of the converter at rated point to 98.5%, the conduction loss on the device and the DC loss of the winding can be reduced, and the AC loss of the winding can also be reduced by connecting the winding and the device in parallel (Less R) and using low-voltage GaN device with the same Rdson but with smaller NFoM (Less C). Experiments have verified that the full-load efficiency of the DCX part of 2nd generation prototype is greatly improved compared with 1st generation prototype. Specifically, when the rated point is 48V input, the full-load efficiency […]

Analysis and Suppression of Low Frequency Common Mode Noise in Totem-pole PFC（Dec. 2023）

2023-08-15

图腾柱PFC因其高效率、高功率密度的优点，现已广泛应用于数据中心电源等场景。工频管开关动作所引起的电流噪声大小影响着共模滤波器的体积，进而影响图腾柱PFC的功率密度。为了提高功率密度，对图腾柱PFC建立工频管的共模噪声模型，分析得到共模回路阻抗Cps、工频管开关速度Vbus/tr与共模电流最大值iCM_M的数学模型，从而优化滤波器的设计。 Totem-pole PFC has been widely used in applications such as data center power supplies due to its advantages of high efficiency and high power density. Therefore, the magnitude of the common mode(CM) current caused by the switching change of the line frequency switch affects the volume of the common mode filter, which in turn affects the power density of the totem-pole PFC. In order to improve the power density, the CM current noise model of the line frequency switch was established for the totem-pole PFC, and the mathematical model of impedance Cps, switching speed Vbus/tr and CM current iCM_M was analyzed, and the scheme of the relevant parameters and filter parameter design was obtained.

Analysis and Suppression of High Frequency Common Mode Noise of 240W Adapter（Dec. 2023）

2023-12-15

由于影响240W适配器中的共模滤波器大小的主要原因来自于DCX拓扑所产生高频共模噪声，对此建立针对高频噪声的数学模型。针对多元胞多个噪声源的特点，通过控制的策略减小共模电流噪声。 Since the main factor affecting the volume of the common-mode filter in the 240W adapter comes from high-frequency common-mode(CM) noise, CM current noise model of the high-frequency switch was established and the mathematical equations were obtained. In view of the characteristics of multiple noise sources, a control strategy is used to suppress the CM current noise.

Full Quadrant Dynamic On-Resistance Test Methods and Test Circuit for GaN Devices（Dec. 2023）

2023-12-26

GaN开关器件因其材料特性优异，在电力电子领域现已得到广泛应用。由于表面陷阱以及缓冲层陷阱的存在，现阶段的GaN器件存在动态导通电阻衰退问题。在器件开通之后，其导通电阻将会高于其静态导通电阻值，并随着开通时间的增加而逐渐恢复。目前对于GaN器件动态导通电阻的学术研究存在着一定的局限：（1）在具有半桥结构的拓扑中，构成半桥桥臂的一对开关管可能分别工作于第一象限和第三象限，而现有的测试电路多设计于第一象限模式进行测试；（2）目前市场上的GaN器件主要分为肖特基门极和欧姆门极两种结构，它们在不同工况下的动态电阻表现需要分别评估。为应对现有研究的局限性，ZJU-PMIC团队提出了集第一象限、第三象限测试于一体的全象限GaN器件动态导通电阻测试电路，并配套提出了一种准确有效的动态电阻测试方法，以评估不同技术路线的600/650V GaN器件的动态性能。 GaN devices have been widely used in the field of power electronics due to their excellent material properties. Due to the presence of surface traps and buffer layer traps, GaN devices suffer from dynamic resistance degradation. After the device is turned on, its on-resistance will be higher than its static resistance value and gradually recover with increasing on-time. At present, there are certain limitations in academic research on the dynamic on-resistance of GaN devices: (1) in topologies with a half bridge structure, a pair of switching tubes that make up the half bridge arm may operate in the first and third quadrants respectively, while existing testing circuits are mostly designed for testing in the first quadrant mode; (2) At present, GaN devices are mainly divided into two structures: Schottky gate and Ohmic gate, and their dynamic resistance performance under different operating conditions needs to be evaluated […]

wide voltage range high efficiency high density cellular DC-DC module（Dec. 2023）

2023-12-24

具备宽输入、输出电压范围的DC-DC模块能够满足多元应用场景需求，但会导致更大的器件电压应力、电流应力和电感伏秒，从而使得器件损耗、电感体积和损耗优化困难，制约了高效高密度的实现。本工作基于多电平技术和元胞化技术，提出了级联多电平Boost（Cascaded Multilevel Boost，CMBo）调压、元胞化DCX隔离的两级方案，降低了高电气应力导致的器件和磁性元件损耗。变频谐振驱动变压器实现DCX的多路隔离驱动，大幅减少驱动损耗和占板面积。 DC-DC modules with a wide input and output voltage range can meet the needs of multiple applications, but will lead to greater device voltage stress, current stress and inductor Volt-Sec, which makes device loss, inductor volume and loss optimization difficult, restricting the realization of high efficiency and high power density. Based on Multilevel technology and cellular technology, a two-stage scheme of Cascaded Multilevel Boost (CMBo) for voltage regulation and cellular DCX for isolation is proposed in this work, which reduces the loss of devices and magnetic components caused by high electrical stress. Frequency adjustable resonant drive transformer realizes multi-channel isolated drive of cellular DCX, greatly reducing drive loss and footprint. Fig. 1 Topology of two-stage cellular DC-DC Fig. 2 Two-stage cellular DC-DC prototype Fig. 3 Measured efficiency of two-stage cellular DC-DC