Medium- and high-voltage high-power power electronic equipment is ubiquitous in modern industry, such as large-capacity data centers, super charging stations, flexible DC transmission, and GF equipment. However, the withstand voltages of common commercial IGBTs and silicon carbide MOSFETs are 6.5kV and 1.7kV, respectively, so a single semiconductor power device cannot be directly applied to medium- and high-voltage occasions. Connecting multiple low-voltage power devices in series to meet voltage level requirements is the most direct method to solve the device withstand voltage problem.

The device series connection method has advantages such as simple circuit structure and fewer devices used, and it is highly scalable and can be applied to various circuits. At the same time, it avoids the problem of excessively large passive component volume.

However, device series connection also introduces new problems. The foremost is how to achieve voltage balancing among the series-connected devices, that is, voltage equalization. This includes two aspects: first, static voltage balancing, that is, when the devices are not conducting, the voltages borne by the series-connected devices are balanced; second, during the turn-on and turn-off instants of the devices, the voltages of the power devices can also achieve dynamic balancing. The causes of device voltage imbalance can be divided into two aspects: first, differences in internal device parameters, such as leakage current, threshold voltage, and parasitic capacitance parameters; second, external parameters, such as driving delay of signals, parasitic inductance on the line, and voltage imbalance caused by different temperatures. Power devices may be broken down due to overvoltage, making the devices unusable. Therefore, how to maintain voltage balancing of series-connected devices has become a key issue in research.

An Active Clamping Circuit Using Negative Current for Energy Recovery

ZJU-PMIC proposed an active clamping circuit using negative current for energy recovery, as shown in Figure 1. When the voltage across the power device is greater than the voltage across capacitor C, the voltage is clamped at Vc, ensuring that the device is not overvoltage. During the dead time, the auxiliary switch is turned on, and the negative current is used for discharge. The accumulated electrical energy is fed back to the DC bus, and conduction during the dead time does not affect the normal operation of the main power circuit.

Figure 1 An active clamping circuit module

In medium-voltage applications, due to the large number of power devices and necessary insulation clearances, the DC side of the VSC generates 1–2 μH of parasitic inductance. Therefore, the ACM capacitor exhibits relatively large voltage fluctuations when handling large currents. Consider a 20kV three-phase VSC, with 24 power devices connected in series per arm (rated voltage 1.2kV), a DC loop parasitic inductance of 2μH, and an ACM capacitance of 10μF. When the switching frequency is 20kHz, the PLECS simulation results under different load conditions are shown in Figure 2. When the power reaches 3MW, the ACM capacitor voltage ripple is too high.

Figure 2 PLECS simulation results of a 20kV three-phase inverter

Ripple Suppression Strategy Based on Positive Voltage Difference Discharge

To suppress the ACM capacitor ripple, the research group proposed a ripple suppression strategy based on positive voltage difference discharge. Its equivalent circuit and key waveform timing are shown in Figure 3.

Figure 3 Positive voltage difference discharge: (a) equivalent circuit diagram and (b) key waveforms

The core idea of ripple suppression is to promptly release the commutation charging amount in each switching cycle, so that the charging amount that the clamping capacitor needs to handle or withstand is reduced from accumulation over one power-frequency cycle to one switching cycle.

During the half-cycle of positive current, the clamping capacitor charges in each switching cycle, and this process mainly occurs at the turn-off instant of the upper-arm main switch. When the lower-arm main switch is turned on, we turn on all auxiliary switches of the upper arm. As shown in the equivalent circuit, all clamping capacitors are inserted into the circuit. We analyze the loop formed by the DC bus and the upper and lower arms, that is, the black loop in the equivalent circuit. As long as the sum of the clamping capacitor voltages is greater than the bus voltage at this time, the voltage difference can be used to recover the energy in the clamping capacitors back to the DC bus.

Through this method, the voltage ripple can be greatly reduced. The voltage ripple at this time is several orders of magnitude smaller than the original power-frequency voltage ripple.

Test Circuit and Experimental Verification

The back-to-back test circuit consists of a bridge arm under test and a controlled bridge arm. The driving signal of the bridge arm under test is an SPWM wave, used to test the performance of the series-connected modules. The controlled bridge arm regulates the duty cycle of each switching cycle so that the midpoint current iac of the bridge arm under test tracks the set sinusoidal current. m1 and m2 are the modulation signals of the bridge arm under test and the controlled bridge arm, respectively. By phase-shifting the modulation wave m1, the modulation wave signal m2 of the controlled bridge arm is generated.

Figure 4 also shows the vector relationship of the circuit, m1-m=m2. The inductor voltage VL is in phase with the modulation signal m, and the inductor current iac lags the inductor voltage by 90°, so the inductor current is in phase with the modulation signal m1 of the bridge arm under test. Through this principle, a current in phase with the modulation signal m1 of the bridge arm under test can be generated on the inductor. The power cycle is completed between the bridge arm under test and the controlled bridge arm, so energy can be recovered, and the power supply energy consumption is only the power device loss and circuit parasitic resistance loss.

Figure 4 Back-to-back test circuit

Under the test condition of 1500V/50A, the experimental waveforms with and without voltage difference discharge were compared.

In Figure 5(a), using the original voltage balancing method, when the bridge arm current is positive, the ACM capacitor voltage continues to rise. When iac = 50A, its voltage ripple rises to 70V, with a peak value of 320V. In Figure 5(b), because the proposed discharge method is independent of the AC current, when the bridge arm current is positive, the ACM voltage ripple is significantly reduced. The peak value is about 260V and remains basically unchanged as iac increases.

Figure 5 Voltage waveforms of the clamping capacitor when the AC current changes from 10A to 50A

The voltage was raised to 3kV to observe the corresponding clamping capacitor voltage waveforms, and the prototype efficiency was analyzed. As shown in Figure 7, good suppression of voltage ripple can still be observed at 3kV.

Figure 7 Voltage waveforms of three clamping capacitors at 3kV

Figure 8 shows the prototype efficiency. Comparing whether positive voltage difference discharge is added, the loss does not increase significantly, and the peak efficiency of the prototype is 98.9%. Therefore, the proposed method does not cause a significant impact on prototype efficiency.

Figure 8 Loss and efficiency analysis of the prototype with and without voltage difference discharge at 3kV

References

[1] Gao, Z.; Shao, S.; Cui, W.; Wu, Y.; Zhang, J.; Sheng, K. A Control Strategy for Reducing Voltage Ripples in Series-Connected SiC MOSFETs Using Active Clamping Modules in High Power VSCs. IEEE Transactions on Power Electronics 2024, 39 (10), 12149–12155.

Author: Jiang Yibo